| BODY HEIGHT | 0.035 INCHES MINIMUM AND 0.050 INCHES MAXIMUM |
| BODY LENGTH | 0.250 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| BODY WIDTH | 0.140 INCHES MINIMUM AND 0.150 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 2 GATE, NAND |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND HIGH SPEED AND POSITIVE OUTPUTS AND W/TOTEM POLE OUTPUT AND MEDIUM POWER |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | GLASS AND METAL |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| MAXIMUM POWER DISSIPATION RATING | 396.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| PRECIOUS MATERIAL AND LOCATION | BODY AND TERMINAL SURFACES GOLD |
| PRECIOUS MATERIAL | GOLD |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TEST DATA DOCUMENT | 03640-6088471 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 10.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 10.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |