| BODY HEIGHT | 0.008 INCHES MINIMUM AND 0.100 INCHES MAXIMUM |
| BODY LENGTH | 0.337 INCHES MINIMUM AND 0.350 INCHES MAXIMUM |
| BODY WIDTH | 0.200 INCHES MINIMUM AND 0.300 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-004-AA JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 3 GATE, NAND |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND W/TOTEM POLE OUTPUT |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | TRIPLE 3 INPUT |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 120.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TIME RATING PER CHACTERISTIC | 22.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | -1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE |