| BODY HEIGHT | 0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM |
| BODY LENGTH | 0.240 INCHES MINIMUM AND 0.275 INCHES MAXIMUM |
| BODY WIDTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-86 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, CLOCKED |
| FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND POSITIVE OUTPUTS AND HIGH SPEED AND W/ENABLE AND NEGATIVE EDGE TRIGGERED AND RESETTABLE |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | 8 INPUT |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 110.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TEST DATA DOCUMENT | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| TIME RATING PER CHACTERISTIC | 11.00 NANOSECONDS NOMINAL PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 9.00 NANOSECONDS NOMINAL PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | -0.5 VOLTS MAXIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE |