| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 2 GATE, NAND |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND HIGH SPEED AND SCHOTTKY AND W/TOTEM POLE OUTPUT |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 99.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TEST DATA DOCUMENT | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| TIME RATING PER CHACTERISTIC | 6.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 7.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |