| BODY HEIGHT | 0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM |
| BODY LENGTH | 0.240 INCHES MINIMUM AND 0.275 INCHES MAXIMUM |
| BODY WIDTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-86 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 1 FLIP-FLOP, J-K/R-S, CLOCKED, MASTER SLAVE AND 1 FLIP-FLOP, PULSE TRIGGERED |
| FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND AC COUPLED AND MEDIUM SPEED AND MEDIUM POWER AND POSITIVE OUTPUTS AND W/CLEAR AND NEGATIVE EDGE TRIGGERED AND EDGE TRIGGERED |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | 6 INPUT |
| MAXIMUM POWER DISSIPATION RATING | 34.0 MILLIWATTS |
| OPERATING TEMP RANGE | +0.0 TO 75.0 CELSIUS |
| OUTPUT LOGIC FORM | DIODE-TRANSISTOR LOGIC |
| PRECIOUS MATERIAL | GOLD |
| PRECIOUS MATERIAL AND LOCATION | TERMINALS GOLD |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL SURFACE TREATMENT | GOLD |
| TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| TIME RATING PER CHACTERISTIC | 30.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 30.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |