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National Stock Number:
5962-01-137-6220
Federal Supply Class:
5962
National Item Identification Number:
011376220
Description:
MICROCIRCUIT,DIGITAL
Detail:
A microcircuit specifically designed to generate, modify, or process electrical signals which operate with two distinct or binary states. These states are commonly referred to as on and off, true and false, high and low, or 1 and 0.
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Manufacturer Information:
| 1820-0961 | 28480 | HEWLETT-PACKARD COMPANY | | 1820-2031 | 28480 | HEWLETT-PACKARD COMPANY | | 4021BDMQB | 07263 | FAIRCHILD SEMICONDUCTOR CORP | | 5962-7901201BEB | 67268 | DLA LAND AND MARITIME DBA ENGINEERING AND TECHNICAL SUPPORT DIV DOCUMENT STANDARDIZATION DIVISION (STANDARD MICROCIRCUIT | | 5962-7901201BEX | 67268 | DLA LAND AND MARITIME DBA ENGINEERING AND TECHNICAL SUPPORT DIV DOCUMENT STANDARDIZATION DIVISION (STANDARD MICROCIRCUIT | | 79012 | 67268 | DLA LAND AND MARITIME DBA ENGINEERING AND TECHNICAL SUPPORT DIV DOCUMENT STANDARDIZATION DIVISION (STANDARD MICROCIRCUIT | | MC14021BALD | 04713 | FREESCALE SEMICONDUCTOR, INC. | | MC14021BBEBS | 04713 | FREESCALE SEMICONDUCTOR, INC. | | SCL4021BC | 31019 | ALLEGRO MICROSYSTEMS INC | | CD4021BD/3 | 34371 | RENESAS ELECTRONICS AMERICA INC | | CD4021BF | 34371 | RENESAS ELECTRONICS AMERICA INC | | B4028478-11 | 56996 | DEPARTMENT OF THE ARMY HQ UNITED STATES ARMY COMMUNICATIONS RESEARCH AND DEVELOPMENT COMMAND | | 7901201EA | 67268 | DLA LAND AND MARITIME DBA ENGINEERING AND TECHNICAL SUPPORT DIV DOCUMENT STANDARDIZATION DIVISION (STANDARD MICROCIRCUIT | | 7901201EB | 67268 | DLA LAND AND MARITIME DBA ENGINEERING AND TECHNICAL SUPPORT DIV DOCUMENT STANDARDIZATION DIVISION (STANDARD MICROCIRCUIT | | SCL4021BD | 31019 | ALLEGRO MICROSYSTEMS INC |
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Techincal Specification:
| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.185 INCHES MAXIMUM | | BODY LENGTH | 0.840 INCHES MAXIMUM | | BODY WIDTH | 0.220 INCHES MINIMUM AND 0.310 INCHES MAXIMUM | | CASE OUTLINE SOURCE AND DESIGNATOR | D-2 MIL-M-38510 | | DESIGN FUNCTION AND QUANTITY | 1 SHIFT REGISTER, PARALLEL IN, SERIES OUT | | FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND ASYNCHRONOUS AND SYNCHRONOUS AND LOW POWER | | INCLOSURE CONFIGURATION | DUAL-IN-LINE | | INCLOSURE MATERIAL | CERAMIC AND GLASS | | INPUT CIRCUIT PATTERN | 8 STAGE AND 9 INPUT | | OUTPUT LOGIC FORM | COMPLEMENTARY-METAL OXIDE-SEMICONDUCTOR LOGIC | | MAXIMUM POWER DISSIPATION RATING | 500.0 MILLIWATTS | | OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS | | STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS | | TEST DATA DOCUMENT | 14933-79012 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) | | TIME RATING PER CHACTERISTIC | 750.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 750.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
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