| DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K |
| BODY HEIGHT | 0.180 INCHES NOMINAL |
| BODY LENGTH | 0.755 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |
| BODY WIDTH | 0.245 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| FEATURES PROVIDED | HERMETICALLY SEALED AND LOW POWER AND SCHOTTKY AND W/CLEAR AND W/CLOCK |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| PROPRIETARY CHARACTERISTICS | PACS |
| OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 7.0 VOLTS MAXIMUM POWER SOURCE |
| STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| TERMINAL TYPE AND QUANTITY | 14 PRINTED CIRCUIT |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TEST DATA DOCUMENT | 55974-3596443 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 20.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 20.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |