| BODY HEIGHT | 0.064 INCHES MINIMUM AND 0.100 INCHES MAXIMUM |
| BODY LENGTH | 0.342 INCHES MINIMUM AND 0.358 INCHES MAXIMUM |
| BODY WIDTH | 0.342 INCHES MINIMUM AND 0.358 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | C-2 MIL-M-38510 |
| DESIGN FUNCTION AND QUANTITY | 2 GATE, NAND |
| FEATURES PROVIDED | LOW POWER AND SCHOTTKY AND MONOLITHIC |
| INCLOSURE CONFIGURATION | LEADLESS FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC AND METAL |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TERMINAL TYPE AND QUANTITY | 20 LEADLESS |
| TEST DATA DOCUMENT | 96906-MIL-M-38510 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| TIME RATING PER CHACTERISTIC | 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 7.0 VOLTS MAXIMUM POWER SOURCE |