| DESIGN FUNCTION AND QUANTITY | 3 GATE, NAND |
| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.185 INCHES MAXIMUM |
| BODY LENGTH | 0.796 INCHES MAXIMUM |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.310 INCHES MAXIMUM |
| FEATURES PROVIDED | HERMETICALLY SEALED AND BURN IN AND MONOLITHIC |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC |
| INPUT CIRCUIT PATTERN | TRIPLE 3 INPUT |
| PROPRIETARY CHARACTERISTICS | PACS |
| MAXIMUM POWER DISSIPATION RATING | 19.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 7.0 VOLTS MAXIMUM POWER SOURCE |
| STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| TERMINAL TYPE AND QUANTITY | 14 PRINTED CIRCUIT |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TEST DATA DOCUMENT | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |